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IRFR9220, IRFU9220
Data Sheet July 1999 File Number
4015.3
3.6A, 200V, 1.500 Ohm, P-Channel Power MOSFETs
These are advanced power MOSFETs designed, tested, and guaranteed to withstand a specific level of energy in the avalanche breakdown mode of operation. These are P-Channel enhancement-mode silicon gate power fieldeffect transistors designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high-power bipolar switching transistors requiring high speed and low gate-drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17502.
Features
* 3.6A, 200V * rDS(ON) = 1.500 * Temperature Compensating PSPICE(R) Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Symbol
D
Ordering Information
PART NUMBER IRFR9220 IRFU9220 PACKAGE TO-252AA TO-251AA BRAND IF9220 IF9220
G
NOTE: When ordering use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, e.g., IRFR92209A.
S
Packaging
JEDEC TO-251AA
SOURCE DRAIN GATE GATE SOURCE DRAIN (FLANGE) DRAIN (FLANGE)
JEDEC TO-252AA
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
IRFR9220, IRFU9220
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified IRFR9220, IRFU9220 -200 -200 20 3.6 Refer to Peak Current Curve Refer to UIS Curve 42 0.33 -55 to 150 300 260 UNITS V V V A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
W W/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qgd Qgs CISS COSS CRSS RJC RJA VGS = 0 to -10V VDD = -160V, ID = 3.9A, RL = 41 IG(REF) = 1.45mA TEST CONDITIONS ID = 250A, VGS = 0V VGS = VDS, ID = 250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 150oC VGS = 20V ID = 2.2A, VGS = -10V (Figure 9) VDD = -100V, ID = 3.9A, RL = 24, VGS = -10V, RGS = 18 (Figures 13, 16, 17) MIN -200 -2.0 TYP 8.8 27 7.3 19 20 11 3.3 550 110 33 MAX -4.0 -25 -250 100 1.500 50 50 3.00 100 UNITS V V A A nA W ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W
Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate to Drain Charge Gate to Source Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
VDS = -25V, VGS = 0V, f = 1MHz (Figure 12)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time Reverse Recovery Charge NOTES: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). SYMBOL VSD trr QRR ISD = -3.6A ISD = -3.6A, dISD/dt = -100A/s TEST CONDITIONS MIN TYP 150 0.97 MAX -6.3 300 2.0 UNITS V ns C
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IRFR9220, IRFU9220 Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID , DRAIN CURRENT (A) -3 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TC , CASE TEMPERATURE (oC) 0
Unless Otherwise Specified
-4
-2
-1
25
50
75
100
125
150
TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
ZJC , TRANSIENT THERMAL IMPEDANCE
10
0.5 1 0.2 0.1 0.05 0.1 0.02 0.01 SINGLE PULSE 0.01 10-5 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC 10-3 10-2 10-1 t1 , RECTANGULAR PULSE DURATION (s) 100 101
10-4
FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE
-10 ID , DRAIN CURRENT (A) 100s
IDM , PEAK CURRENT CAPABILITY (A)
-20
-50
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS: VGS = -20V 150 - T C I = I 25 ---------------------- 125
-10 VGS = -10V
1ms -1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) TC = 25oC TJ = MAX RATED -0.1 -1 VDSS MAX = -200V -500
10ms 100ms DC
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION -1 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s)
TC = 25oC 100 101
-10 -100 VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
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IRFR9220, IRFU9220 Typical Performance Curves
-10 IAS , AVALANCHE CURRENT (A)
Unless Otherwise Specified (Continued)
-5 VGS = -8V -4 VGS = -10V VGS = -20V -3 VGS = -6V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC VGS = -5V VGS = -4.5V 0 -1.5 -3.0 -4.5 -6.0 -7.5 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = -7V
STARTING TJ = 25oC
STARTING TJ = 150oC
ID, DRAIN CURRENT (A) 10
-2
If R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) If R 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] -1 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms)
-1
0
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
FIGURE 7. SATURATION CHARACTERISTICS
IDS(ON), DRAIN TO SOURCE CURRENT (A)
-8 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = -15V -6 -55oC
2.5
2.0
PULSE DURATION = 80s VGS = -10V ID = -2.2A
25oC
1.5
-4
1.0
-2
150oC
0.5
0 0 -1 -2 -3 -4 -5 -6 -7 VGS, GATE TO SOURCE VOLTAGE (V)
0 -80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A THRESHOLD VOLTAGE
2.0 ID = 250A 1.5
NORMALIZED GATE
1.5
1.0
1.0
0.5
0.5
0 -80
-40
0
40
80
120
160
0 -80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs TEMPERATURE
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IRFR9220, IRFU9220 Typical Performance Curves
700 600 C, CAPACITANCE (pF) CISS 500 400 300 200 100 0 0 CRSS -5 -10 -15 -20 VDS , DRAIN TO SOURCE VOLTAGE (V) -25 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD COSS
Unless Otherwise Specified (Continued)
-200 VDS , DRAIN TO SOURCE VOLTAGE (V)
-160 RL = 51 IG(REF) = -1.45mA VGS = -10V 0.75 BVDSS 0.75 BVDSS 0.50 BVDSS 0.50 BVDSS 0.25 BVDSS 0.25 BVDSS -40
-8.0
-120
-6.0
-80
-4.0
-2.0
0 20
IG(REF) IG(ACT)
t, TIME (s)
80
IG(REF) IG(ACT)
0.0
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Application Notes AN7254 and AN7260. FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0
+
VDD VDD
0V VGS
DUT tP IAS 0.01
IAS tP BVDSS VDS
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tON td(ON) tr tOFF td(OFF) tf 10% 10%
RL
0
DUT VGS RG
VDD
+
VDS VGS 0
90%
90%
10% 50% PULSE WIDTH 90% 50%
FIGURE 16. SWITCHING TIME TEST CIRCUIT
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
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VGS , GATE TO SOURCE VOLTAGE (V)
VDD = BVDSS
VDD = BVDSS
-10.0
IRFR9220, IRFU9220 Test Circuits and Waveforms
CURRENT REGULATOR
(Continued)
-VDS (ISOLATED SUPPLY)
0 VDS
DUT 12V BATTERY 0.2F 50k 0.3F Qgs D G 0 Ig(REF) IG CURRENT SAMPLING RESISTOR S +VDS ID CURRENT SAMPLING RESISTOR 0 DUT VDD Qgd
VGS
Qg(TOT)
Ig(REF)
FIGURE 18. GATE CHARGE TEST CIRCUIT
FIGURE 19. GATE CHARGE WAVEFORMS
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IRFR9220, IRFU9220 PSPICE Electrical Model
.SUBCKT IRFU9220 2 1 3 CA 12 8 723e-12 CB 15 14 733e-12 CIN 6 8 517e-12
10
REV 9/6/94
RLDRAIN DPLCAP 5 DRAIN 2 LDRAIN RSCL2 RSCL1 + 51 5 51 6 8 VTO + 16 21 MOS1 RIN CIN 8 RSOURCE 7 RLSOURCE 3 SOURCE LSOURCE S1A S2A 14 13 13 S2B CB CA + 6 EGS 8 + EDS 14 5 8 IT 19 VBAT + 15 17 RBREAK 18 12 13 8 S1B ESCL 50 RDRAIN 11 + EBREAK 17 18 MOS2 DBODY DBREAK
DBODY 5 7 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 6 DPLCAPMOD EBREAK 7 11 17 18 -244.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTO 20 6 8 18 1
RLGATE
ESG +
IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.609e-9 LSOURCE 3 7 2.609e-9
GATE 1 LGATE
+
RGATE 9
EVTO 18 20 8
6
-
MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 1.194 RGATE 9 20 2.17 RIN 6 8 1e9 RLDRAIN 2 5 10 RLGATE 1 9 26.09 RLSOURCE 3 7 26.09 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 90.1e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 -0.77 ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/4.6,6))} .MODEL DBDMOD D (IS=2.56e-14 RS=8.09e-2 TRS1=-2.45e-3 TRS2=-1.33e-5 CJO=4.21e-10 TT=1.17e-7) .MODEL DBKMOD D (RS=5.07 TRS1=-1.05e-3 TRS2=1.28e-5) .MODEL DPLCAPMOD D (CJO=170e-12 IS=1e-30 N=10) .MODEL MOSMOD PMOS (VTO=-3.58 KP=1.38 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=1.1e-3 TC2=-2.73e-6) .MODEL RDSMOD RES (TC1=6.95e-3 TC2=2.23e-5) .MODEL RSCLMOD RES (TC1=2.40e-3 TC2=-1.5e-5) .MODEL RVTOMOD RES (TC1=-3.27e-3 TC2=-1.33e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=5.29 VOFF=3.29) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.29 VOFF=5.29) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.1 VOFF=-4.9) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.9 VOFF=0.1)
.ENDS
RVTO
-
-
-
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley.
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IRFR9220, IRFU9220
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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